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panic_handler.rs 3.62 KiB
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#![feature(panic_info_message)]
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#![no_main]
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#![no_std]
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extern crate lpc4370_drivers;
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use rtfm::app;
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// CCU driver
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use lpc4370::ccu1::clk_m4_bus_cfg;
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use lpc4370_drivers::ccu_config;
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// UART driver
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use lpc4370::usart0::{
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    iir::INTIDR,
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    lcr::{BCW, DLABW, PEW, PSW, SBSW, WLSW},
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};
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use lpc4370_drivers::{
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    serial::{Read, Serial, Write as SerialWrite},
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    timer::{InterruptType, Timer},
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};
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static TIMER_PERIOD: u32 = 8192;
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// Panic handler for USART3
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use lpc4370_drivers::{uart_panic_handler, debug::PanicInfo};
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uart_panic_handler!(lpc4370::USART3);
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#[app(device = lpc4370)]
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const APP: () = {
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    static mut TIMER: Timer<lpc4370::TIMER0> = ();
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    #[init]
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    fn init() -> init::LateResources {
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        let mut serial = Serial::<lpc4370::USART3>::new(device.USART3, 0x41, 0x0, 0x0, None);
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        serial.lcr(
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            WLSW::_8_BIT_CHARACTER_LENGTH,
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            SBSW::_1_STOP_BIT,
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            PEW::DISABLE_PARITY_GENERERATION,
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            PSW::ODD_PARITY,
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            BCW::DISABLED,
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            DLABW::DISABLED,
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        );
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        serial.ier(true, false, false, false, false);
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        // Configure timer
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        let timer = Timer::<lpc4370::TIMER0>::new(device.TIMER0);
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        timer.start_timer(false);
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        timer.set_match(0, TIMER_PERIOD);
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        timer.set_prescaler(1024, Some(0));
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        timer.mr0(true, true, false);
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        timer.start_timer(true);
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        // USART3 I/O
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        unsafe {
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            device.SCU.sfsp90_[3].write(|w| w.mode().bits(0x7).epun().bit(true)); // TX
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            device.SCU.sfsp90_[4].write(|w| w.mode().bits(0x7).epun().bit(true).ezi().bit(true)); // RX
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        }
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        // Configure PLL1 for use with UART3
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        unsafe {
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            // Select the IRC as BASE_M4_CLK source
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            device.CGU.base_m4_clk.write(|w| w.clk_sel().bits(0x1));
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            // Enable the crystal oscillator
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            device.CGU.xtal_osc_ctrl.modify(|_, w| w.hf().bit(false));
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            device.CGU.xtal_osc_ctrl.modify(|_, w| w.enable().bit(false));
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            // Wait 250us
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            for i in 0 .. 3_000 {
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                core::ptr::read_volatile(&i);
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} device.CGU.pll1_ctrl.write(|w| w .pd().bit(false) .clk_sel().bits(0x6) // Select the crystal oscillator as clock source .msel().bits(20) .nsel().bits(1) // Select the M and N divider values .psel().bits(0) .fbsel().bit(true) .bypass().bit(false) .direct().bit(false)); // Wait for the PLL to lock while !device.CGU.pll1_stat.read().lock().bit() {} // Set PLL1 p-divider to divide by 2 (DIRECT=0; PSEL=0) device.CGU.pll1_ctrl.modify(|_, w| w.direct().bit(false).psel().bits(0x0)); // Select PLL1 as base_m4_clk source device.CGU.base_m4_clk.modify(|_, w| w.clk_sel().bits(0x09)); // Wait for 50us for i in 0 .. 600 { core::ptr::read_volatile(&i); } // Enable direct output mode device.CGU.pll1_ctrl.modify(|_, w| w.direct().bit(true)); // Enable clock on UART3 device.CGU.base_uart3_clk.write(|w| w.clk_sel().bits(0x09)); // configure crystal oscillator } unsafe { PANIC_UART = Some(serial); } init::LateResources { TIMER: timer, } } #[idle] fn idle() -> ! { loop {} } #[interrupt(resources = [TIMER])] fn TIMER0() { panic!("this is being printed over UART"); resources .TIMER .clear_interrupt(InterruptType::MatchChannel, 0); } };