This MR implements the blocking::delay traits from embedded_hal
. The implementation expects the BASE_M4_CLK
in its default configuration of 96Mhz [0] as the branch clocks in use, CLK_M4_TIMER{0,1,2,3}
, derive from it. An addition of some abstraction for the clock tree configuration (from which frequencies can be queried) would greatly improve this module.
Question regarding the traits: doc for delay_ms(&mut self, ms: UXX)
says: "Pauses execution for ms
milliseconds". Does this mean that execution should be paused for exactly ms
milliseconds, or at least ms
milliseconds? [1]
[0] I'm not fully convinced of this frequency. The reference manual seems to say that BASE_M4_CLK
uses the 12MHz internal RC (IRC) oscillator as input, but also says in multiple places that "CPU clock = 96Mhz", depending on boot mode (see §13.2.1, for example). Experimentally, 96MHz seems to be the correct configuration.
[1] Given the description of the hardware timers (§32) — and consequently from [0] — timer prescalers and match values are also of an experimental nature. Because TC
(§32.6, table 786) increments one "tick" after a match, we should subtract 1 from the currently configured prescaler value, but this yields a execution pause of 997.60ms (incl. overhead) while the current implementation yields 1.0078ms. Additionally, delay_us(1)
, pauses execution for 2.3822µs. Are these delays within expected boundaries?